The Inverter is the basic building block of all digital designs . One can design more complex and intricate structure by understanding the properties and operations of the inverter. The analysis of the inverter can be extended to explain the behavior of more complex gates such as NAND and NOR which are known to be universal gates and thus form the building blocks for other circuits such as multiplier and processors.
The performance and power consumption of a design is greatly affected by the choice of technology and the design style.The scaling of the technology also affects various properties of the inverter.
First we describe the basic operation of an inverter then we discuss the various properties of the inverter.
Fig shows a CMOS inverter which can be modeled as a switch wiht a finite on resistance Ron when
|VGS| < |VT| the switch is open
VGS > VT the transistor behaves as a finite resistance
This leads to the following interpretation of the inverter
i.e. When Vin is high(equal to VDD) NMOS is on and PMOS is off this leads to a direct dc path b/w Vout and Ground node resulting in a steady state value of ov
On the other hand , when the input voltage is low (0V),NMOS is off and PMOS is on respectively. Thus a path exists b/w VDD and Vout yielding a high output voltage. Since no path exists b/w supply and ground in the steady state operation. Consequently the inverter does not consume any static power(except due to leakage).
The voltage-transfer characteristics of the inverter can be deduced from the load-line plots, by superimposing the current characteristics of the NMOS and PMOS devices. fig shows the voltage characteristics of the CMOS inverter.
Region I
In this case when we apply an input voltage between 0 and VTN. The PMOS device is on since a low voltage is being applied to it. The NMOS is off and turns into a large resistor. Since the NMOS device is off, there is no current flow through either device. VDD is available at the Vout terminal since no current is going through the PMOS device and thus no voltage is being dropped across it.
The PMOS device is forward biased (VSG > -VTP) and therefore on. This MOSFET is in the linear region (VSD<=VSG+VTP=VDD-Vo+VTP).
The NMOS device is cut off since the input voltage is below VTN (Vin=VGS<VTN).
The power dissipation is zero.
Region II
Here we raise the input voltage above VTN. We find that the PMOS device remains in the linear region since it still has adequate forward bias. The NMOS turns on and jumps immediately into saturation since it still has a relatively large VDS across it.
The PMOS device is in the linear region (VSD<=VSG+VTP).
The NMOS device is in the saturation region (Vin=VDS>=VGS-VTN=Vout-VTN).
Current now flows through both devices. Power dissipation is no longer zero.
The maximum allowable input voltage at the low logic state (VIL) occurs in this region. VIL is the value of Vin at the point where the slope of the VTC is -1. Put another way, VIL occurs at (dVout/dVin)=-1.
Region III
In the middle of this region there exists a point where Vin=Vout. We label this point VM and identify it as the gate threshold voltage. The voltage dropped across the NMOS device equals the voltage dropped across the PMOS device when the input voltage is VM. For a very short time, both devices see enough forward bias voltage to drive them to saturation.
The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vout+VTP).
The NMOS device is in the saturation region (VDS>=VGS-VTN=Vout-VTN).
Power dissipation reaches a peak in this region, namely at where VM=Vin=Vout.
Region IV
Region IV occurs between an input voltage slightly higher than VM but lower than VDD-VTP. Now the NMOS device is conducting in the linear region, dropping a low voltage across VDS. Since VDS is relatively low, the PMOS device must pick up the tab and drop the rest of the voltage (VDD-VDS) across its VSD junction. This, in turn, drives the PMOS into saturation. This region is effectively the reverse of region II.
The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vout+VTP).
The NMOS device is forward biased (Vin=VGS > VTN) and therefore on. This MOSFET is in the linear region (Vin=VDS<=VGS-VTN=Vout-VTN).
The minimum allowable input voltage at the logic high state (VIH) occurs in this region. VIH occurs at the point where the slope of the VTC is –1 (dVout/dVin)=-1.
Region V
The NMOS wants to conduct but its drain current is severely limited due to the PMOS device only letting through a tiny leakage current. The PMOS is out to lunch since it is seeing a positive drive but it is already positive enough and has no use for more. This drain current let through by the PMOS is too small to matter in most practical cases so we let ID=0. With this information we can conclude that VDS=Vo=0 V for the NMOS since no current is going through the device. We have, in effect, sent in VDD and found the inverter’s output to be zero volts. For CMOS inverters, VOH=VDD. VOL is defined to be the output voltage of the inverter at an input voltage of VOH. We have just proven that VOL=0.
The PMOS device is cut off when the input is at VDD (VSG=0 V).
The NMOS device is forward biased (Vin=VGS > VTN) and therefore on. This MOSFET is in the linear region (Vin=VDS<=VGS-VTN).
The total power dissipation is zero just as in region I
The smaller the gate, the higher the integration density and the smaller the die size. Die size directly relates to the fabrication cost of a design. Smaller gates tend also to be faster, as the total gate capacitance often scales with the area.
The performance and power consumption of a design is greatly affected by the choice of technology and the design style.The scaling of the technology also affects various properties of the inverter.
First we describe the basic operation of an inverter then we discuss the various properties of the inverter.
The Static CMOS Inverter
 |
| Static CMOS inverter, VDD stands for the supply voltage. |
|VGS| < |VT| the switch is open
VGS > VT the transistor behaves as a finite resistance
This leads to the following interpretation of the inverter
 |
| Switch Model for the CMOS inverter |
i.e. When Vin is high(equal to VDD) NMOS is on and PMOS is off this leads to a direct dc path b/w Vout and Ground node resulting in a steady state value of ov
On the other hand , when the input voltage is low (0V),NMOS is off and PMOS is on respectively. Thus a path exists b/w VDD and Vout yielding a high output voltage. Since no path exists b/w supply and ground in the steady state operation. Consequently the inverter does not consume any static power(except due to leakage).
Points to remember
- The high and low output levels equals VDD and GND, respectively.i.e. the voltage swing is equal to the supply voltage. This results in high noise margins(as explained later).
- The input impedance of the CMOS inverter is extremely high, as the gate of an MOS transistor is an insulator and draws no dc current. Thus can have theoretically infinite fanout .
- In steady state there is path with finite resistance between the output and either VDD of GND. Thus it has a low output impedance which makes it less sensitive to noise and disturbances.
Voltage Transfer Characteristics(VTC)
 |
| VTC of static CMOS inverter for each region the modes of transistor are annotated |
In this case when we apply an input voltage between 0 and VTN. The PMOS device is on since a low voltage is being applied to it. The NMOS is off and turns into a large resistor. Since the NMOS device is off, there is no current flow through either device. VDD is available at the Vout terminal since no current is going through the PMOS device and thus no voltage is being dropped across it.
The PMOS device is forward biased (VSG > -VTP) and therefore on. This MOSFET is in the linear region (VSD<=VSG+VTP=VDD-Vo+VTP).
The NMOS device is cut off since the input voltage is below VTN (Vin=VGS<VTN).
The power dissipation is zero.
Region II
Here we raise the input voltage above VTN. We find that the PMOS device remains in the linear region since it still has adequate forward bias. The NMOS turns on and jumps immediately into saturation since it still has a relatively large VDS across it.
The PMOS device is in the linear region (VSD<=VSG+VTP).
The NMOS device is in the saturation region (Vin=VDS>=VGS-VTN=Vout-VTN).
Current now flows through both devices. Power dissipation is no longer zero.
The maximum allowable input voltage at the low logic state (VIL) occurs in this region. VIL is the value of Vin at the point where the slope of the VTC is -1. Put another way, VIL occurs at (dVout/dVin)=-1.
Region III
In the middle of this region there exists a point where Vin=Vout. We label this point VM and identify it as the gate threshold voltage. The voltage dropped across the NMOS device equals the voltage dropped across the PMOS device when the input voltage is VM. For a very short time, both devices see enough forward bias voltage to drive them to saturation.
The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vout+VTP).
The NMOS device is in the saturation region (VDS>=VGS-VTN=Vout-VTN).
Power dissipation reaches a peak in this region, namely at where VM=Vin=Vout.
Region IV
Region IV occurs between an input voltage slightly higher than VM but lower than VDD-VTP. Now the NMOS device is conducting in the linear region, dropping a low voltage across VDS. Since VDS is relatively low, the PMOS device must pick up the tab and drop the rest of the voltage (VDD-VDS) across its VSD junction. This, in turn, drives the PMOS into saturation. This region is effectively the reverse of region II.
The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vout+VTP).
The NMOS device is forward biased (Vin=VGS > VTN) and therefore on. This MOSFET is in the linear region (Vin=VDS<=VGS-VTN=Vout-VTN).
The minimum allowable input voltage at the logic high state (VIH) occurs in this region. VIH occurs at the point where the slope of the VTC is –1 (dVout/dVin)=-1.
Region V
The NMOS wants to conduct but its drain current is severely limited due to the PMOS device only letting through a tiny leakage current. The PMOS is out to lunch since it is seeing a positive drive but it is already positive enough and has no use for more. This drain current let through by the PMOS is too small to matter in most practical cases so we let ID=0. With this information we can conclude that VDS=Vo=0 V for the NMOS since no current is going through the device. We have, in effect, sent in VDD and found the inverter’s output to be zero volts. For CMOS inverters, VOH=VDD. VOL is defined to be the output voltage of the inverter at an input voltage of VOH. We have just proven that VOL=0.
The PMOS device is cut off when the input is at VDD (VSG=0 V).
The NMOS device is forward biased (Vin=VGS > VTN) and therefore on. This MOSFET is in the linear region (Vin=VDS<=VGS-VTN).
The total power dissipation is zero just as in region I
Definitions and Properties
Area and Complexity
The smaller the gate, the higher the integration density and the smaller the die size. Die size directly relates to the fabrication cost of a design. Smaller gates tend also to be faster, as the total gate capacitance often scales with the area.
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